Changeset 3999

Timestamp:

10/10/08 04:27:31 (1 month ago)

Author:

Don Clugston

Message:

Extended the list of features.

Files:

• trunk/tango/math/internal/Cache.d (modified) (6 diffs)

trunk/tango/math/internal/Cache.d

@@ -83 +83 @@
-    char[] vendor()     {return vendorID;}
-    /// Returns processor string, for display purposes only
-
+    
-    
-    /// The data caches. If there are fewer than 5 physical caches levels,
-    /// the remaining levels are set to uint.max (== entire memory space)
-    CacheInfo[5] datacache;
-
-
+ on-chip
+onChip
-    /// Is MMX supported?
-    bool mmx()          {return (features&MMX_BIT)!=0;}
@@ -154 +154 @@
-    /// (1) Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2).
-    /// (2) AMD Athlon (K7, K8, K10).
-
-
-
-
+
+
+
+
+
+
-    ///
-    /// Within each dynasty, the optimisation techniques are largely
@@ -171 +173 @@
-
-private:    
+public:
+    /// Processor type (vendor-dependent).
+    /// This should be visible ONLY for display purposes.
+    uint stepping, model, family;
+    uint numCacheLevels = 1;
+    private:
-    bool probablyIntel; // true = _probably_ an Intel processor, might be faking
-    bool probablyAMD; // true = _probably_ an AMD processor
-    /// Processor type (vendor-dependent).
-    /// This should be visible ONLY for display purposes.
-    uint stepping, model, family;
-    char [12] vendorID;
-    char [] processorName;
-    char [48] processorNameBuffer;
-    uint numCacheLevels = 1;
-    uint features = 0;     // mmx, sse, sse2, hyperthreading, etc
-popcnt, 
-dn
+
+DN
-    uint amdmiscfeatures = 0; // sse4a, sse5, svm, etc
-    uint maxCores = 1;
@@ -189 +193 @@
-    bool hyperThreadingBit()    { return (features&HTT_BIT)!=0;}
-    
-
+ CPUID1_EDX
-    enum : uint
-    {
@@ -204 +208 @@
-        IA64_BIT = 1<<30
-    }
-  
+CPUID1_ECX
-    enum : uint
-    {
-        SSE3_BIT = 1,
+        PCLMULQDQ_BIT = 1<<1, // from AVX
-        MWAIT_BIT = 1<<3,
-        SSSE3_BIT = 1<<9,
+        FMA_BIT = 1<<12,     // from AVX
-        CMPXCHG16B_BIT = 1<<13,
-        SSE41_BIT = 1<<19,
-        SSE42_BIT = 1<<20,
-
+
+
+
+
-    }
-/+    
-    // Does it have Cyrix MMX extensions? (This works, but who cares?)
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-+/    
-    // AMD feature flags
@@ -288 +316 @@
-                datacache[level].size=sizes[i];
-                datacache[level].associativity=ways[i];
-
+
+
-                    || (x>=0x66 && x<=0x68) || (x>=0x39 && x<=0x3E) ){
-                    datacache[level].lineSize = 64;