Changeset 3181

Timestamp:

02/14/08 03:41:17 (10 months ago)

Author:

Don Clugston

Message:

Added the proper values for FPU flags for SPARC.

Files:

trunk/tango/math/IEEE.d

r3180	r3181
218	218	INVALID_MASK = 0x01
219	219	}
220		// Don't bother about denormals, they are not supported on ~~all~~ CPUs.
221		//~~const int~~ DENORMAL_MASK = 0x02;
	220	// Don't bother about denormals, they are not supported on most CPUs.
	221	// DENORMAL_MASK = 0x02;
222	222	} else version (PPC) {
223	223	// PowerPC FPSCR is a 32-bit register.
…	…
229	229	INVALID_MASK = 0xF80
230	230	}
231		} else { //SPARC -- not yet implemented
	231	} else { //SPARC FSR is a 32bit register
	232	//(64 bits for Sparc 7 & 8, but high 32 bits are uninteresting).
232	233	enum : int {
233		INEXACT_MASK = 0,
234		UNDERFLOW_MASK = 0,
235		OVERFLOW_MASK = 0,
236		DIVBYZERO_MASK = 0,
237		INVALID_MASK = 0
	234	INEXACT_MASK = 0x020,
	235	UNDERFLOW_MASK = 0x080,
	236	OVERFLOW_MASK = 0x100,
	237	DIVBYZERO_MASK = 0x040,
	238	INVALID_MASK = 0x200
238	239	}
239	240	}
…	…
254	255	}
255	256	} else {
	257	/* SPARC:
	258	int retval;
	259	asm { st %fsr, retval; }
	260	return retval;
	261	*/
256	262	assert(0, "Not yet supported");
257	263	}
…	…
264	270	}
265	271	} else {
	272	/* SPARC:
	273	int tmpval;
	274	asm { st %fsr, tmpval; }
	275	tmpval &=0xFFFF_FC00;
	276	asm { ld tmpval, %fsr; }
	277	*/
266	278	assert(0, "Not yet supported");
267	279	}