Changeset 1381
- Timestamp:
- 12/14/09 08:21:49 (15 years ago)
- Files:
-
- trunk/docsrc/iasm.dd (modified) (3 diffs)
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trunk/docsrc/iasm.dd
r1380 r1381 59 59 L1: ; 60 60 pop EBX ; 61 61 mov pc[EBP],EBX ; // pc now points to code at L1 62 62 } 63 63 -------------- 64 64 65 65 <h2>align $(I IntegerExpression)</h2> 66 66 67 67 $(GRAMMAR 68 68 $(GNAME IntegerExpression): 69 $( I IntegerLiteral)69 $(LINK2 lex.html#IntegerLiteral, $(I IntegerLiteral)) 70 70 $(I Identifier) 71 71 ) 72 72 73 73 $(P Causes the assembler to emit NOP instructions to align the next 74 74 assembler instruction on an $(I IntegerExpression) boundary. 75 75 $(I IntegerExpression) must evaluate at compile time to an integer that is 76 76 a power of 2. 77 77 ) 78 78 79 79 $(P Aligning the start of a loop body can sometimes have a dramatic … … 127 127 -------------- 128 128 129 129 <h2>Opcodes</h2> 130 130 131 131 A list of supported opcodes is at the end. 132 132 <p> 133 133 134 134 The following registers are supported. Register names 135 135 are always in upper case. 136 136 137 <dl><dl> 138 <dt>$(B AL), $(B AH), $(B AX), $(B EAX) 139 <dt>$(B BL), $(B BH), $(B BX), $(B EBX) 140 <dt>$(B CL), $(B CH), $(B CX), $(B ECX) 141 <dt>$(B DL), $(B DH), $(B DX), $(B EDX) 142 <dt>$(B BP), $(B EBP) 143 <dt>$(B SP), $(B ESP) 144 <dt>$(B DI), $(B EDI) 145 <dt>$(B SI), $(B ESI) 146 <dt>$(B ES), $(B CS), $(B SS), $(B DS), $(B GS), $(B FS) 147 <dt>$(B CR0), $(B CR2), $(B CR3), $(B CR4) 148 <dt>$(B DR0), $(B DR1), $(B DR2), $(B DR3), $(B DR6), $(B DR7) 149 <dt>$(B TR3), $(B TR4), $(B TR5), $(B TR6), $(B TR7) 150 <dt>$(B ST) 151 <dt>$(B ST(0)), $(B ST(1)), $(B ST(2)), $(B ST(3)), 152 $(B ST(4)), $(B ST(5)), $(B ST(6)), $(B ST(7)) 153 <dt>$(B MM0), $(B MM1), $(B MM2), $(B MM3), 154 $(B MM4), $(B MM5), $(B MM6), $(B MM7) 155 <dt>$(B XMM0), $(B XMM1), $(B XMM2), $(B XMM3), 156 $(B XMM4), $(B XMM5), $(B XMM6), $(B XMM7) 157 </dl></dl> 137 $(GRAMMAR 138 $(GNAME Register): 139 $(B AL) $(B AH) $(B AX) $(B EAX) 140 $(B BL) $(B BH) $(B BX) $(B EBX) 141 $(B CL) $(B CH) $(B CX) $(B ECX) 142 $(B DL) $(B DH) $(B DX) $(B EDX) 143 $(B BP) $(B EBP) 144 $(B SP) $(B ESP) 145 $(B DI) $(B EDI) 146 $(B SI) $(B ESI) 147 $(B ES) $(B CS) $(B SS) $(B DS) $(B GS) $(B FS) 148 $(B CR0) $(B CR2) $(B CR3) $(B CR4) 149 $(B DR0) $(B DR1) $(B DR2) $(B DR3) $(B DR6) $(B DR7) 150 $(B TR3) $(B TR4) $(B TR5) $(B TR6) $(B TR7) 151 $(B ST) 152 $(B ST(0)) $(B ST(1)) $(B ST(2)) $(B ST(3)) $(B ST(4)) $(B ST(5)) $(B ST(6)) $(B ST(7)) 153 $(B MM0) $(B MM1) $(B MM2) $(B MM3) $(B MM4) $(B MM5) $(B MM6) $(B MM7) 154 $(B XMM0) $(B XMM1) $(B XMM2) $(B XMM3) $(B XMM4) $(B XMM5) $(B XMM6) $(B XMM7) 155 ) 158 156 159 157 <h3>Special Cases</h3> 160 158 161 159 $(DL 162 160 163 161 $(DT $(B lock), $(B rep), $(B repe), $(B repne), 164 162 $(B repnz), $(B repz)) 165 163 $(DD These prefix instructions do not appear in the same statement 166 164 as the instructions they prefix; they appear in their own statement. 167 165 For example: … … 267 265 $(I AsmTypePrefix) $(I AsmExp) 268 266 $(B offsetof) $(I AsmExp) 269 267 $(B seg) $(I AsmExp) 270 268 $(B +) $(I AsmUnaExp) 271 269 $(B -) $(I AsmUnaExp) 272 270 $(B !) $(I AsmUnaExp) 273 271 $(B ~) $(I AsmUnaExp) 274 272 $(I AsmPrimaryExp) 275 273 276 274 $(GNAME AsmPrimaryExp): 277 $( I IntegerConstant)278 $( I FloatConstant)275 $(LINK2 lex.html#IntegerLiteral, $(I IntegerLiteral)) 276 $(LINK2 lex.html#FloatLiteral, $(I FloatLiteral)) 279 277 $(B __LOCAL_SIZE) 280 278 $(B $) 281 $( IRegister)279 $(GLINK Register) 282 280 $(I DotIdentifier) 283 281 284 282 $(GNAME DotIdentifier): 285 283 $(I Identifier) 286 284 $(I Identifier) $(B .) $(I DotIdentifier) 287 285 ) 288 286 289 287 $(P The operand syntax more or less follows the Intel CPU documentation 290 288 conventions. 291 289 In particular, the convention is that for two operand instructions